1. Field of the Invention
The present invention relates to a technique for making a semiconductor device that includes the formation of a silicide layer on a deposited silicon layer.
2. Description of the Prior Art
In the production of integrated circuits (ICs), it has become common practice to form silicide conductor layers. The silicides are compounds comprising a refractory metal and silicon, which may be in the form of deposited polysilicon. The refractory metals commonly used or proposed include titanium, tantalum, tungsten, molybdenum, and cobalt, among others. Such metal silicide layers have relatively high conductivity, and when lithographically patterned, can serve as gate electrodes for field effect transistors, and conductor patterns, referred to as "runners", for interconnecting various circuit elements of the integrated circuit.
For example, referring to FIG. 1, a typical MOS structure comprises a p-type silicon substrate 101. (In the case of a CMOS IC, region 101 could be a p-tub). A n-channel transistor is formed in the substrate, and includes source/drain n+doped regions 103 and 104, having silicide layers 106 and 107 formed thereon, respectively. The gate electrode comprises a doped polysilicon layer 109 and silicide layer 108 overlying a gate oxide 110. The gate sidewalls may be covered by spacers 129 and 130, as in the case of the "lightly doped drain" (LDD) structure. Furthermore, the same conductive layers that form the gate electrode may extend over the field oxide region 120, forming a runner comprising doped polysilicon layer 123 and silicide layer 122. The combination of the doped polysilicon and silicide layers is frequently referred to as the "polycide" structure in the art. Various other applications for silicide layers are known for bipolar and optical devices.
As the lateral dimensions of integrated circuit elements becomes smaller, it is also necessary to reduce the height of various circuit structures. For example, the height of a polycide gate electrode includes the thickness of the deposited polysilicon layer (109) and the silicide layer (108) formed thereon. As lateral dimensions (e.g., gate length) shrink below 1 micrometer, it is typically necessary to reduce the so-called "stack height" of the polycide structure (d1) to less than 1 micrometer, and desirably less than 0.5 micrometers. This is necessary in order to reduce problems relating to etching of relatively thick layers, as well as for preventing excessive step heights that interfere with the formation of overlying circuit elements. However, as the stack height of the gate electrode decreases, the probability increases that shorts will occur between the gate electrode and the adjacent source/drain electrodes during silicide formation. Furthermore, significant problems at the interface between the polysilicon layer and the silicide layer have been observed. These problems have included direct shorts and de- lamination of the silicide layer in some cases. In addition, at small stack heights, the planarity of the gate is reduced, and the surface actually becomes concave, rather than being the ideal planar surface shown for layer 108.
Generally, the deposited polysilicon films have a high degree of [110] preferred crystallographic orientation, and a large variation in stress within the polysilicon layer. In addition, these polysilicon films, when used as a mask for a gate oxide, are more susceptible to ion-channelling in &lt;110&gt; directions during a high energy source/drain ion implant operation. This problem is especially significant for ion implant energies in excess of about 70 keV. It is known that the channeling can be minimized by randomizing the polysilicon orientation. It is also known that most silicide structures exhibit the "snow plow effect" during their formation, where the redistribution of n-type dopant concentration often occurs.
One important criterion of proper circuit operation is the resistance of the conductors used to form runners. Therefore, as both the lateral dimensions and stack height are reduced, the cross-sectional area of the polycide conductors is reduced. This leads to increased electrical resistance of the conductors, which is undesirable in most cases. Therefore, any solution to the problems relating to thin stack heights should not unduly increase the electrical resistance of the polycide conductors.